The present invention relates to the field of read only memory (ROM) cells, and ROM memory architecture providing for a high density and low power consumption.
The present invention is directed to a ROM memory device. A ROM is a read only memory device which programmed during an integrated circuit manufacturing process. Once the ROM has been programmed the data in the ROM is fixed such that the data stored in the ROM can be read, but it cannot be changed. FIG. 1 shows a ROM memory array architecture 100 of the prior art. This architecture includes an array 100 of bit cells, where each bit cell corresponds to an area between a bit line (BL0-BL4) and a word line (WL0-WL3). The ROM array 100 is programed with a combination of ones (1) and zeros (0). A zero (0) is stored in a bit cell of the ROM array 100 by providing an NMOS transistor between a bit line and a word line. For example, by virtue of the fact that a transistor T10 is formed between the bit line BL0 and word line WL1 a 0 is stored in the corresponding bit cell. The word line acts as a gate for NMOS transistor T10 and is electrically coupled to the channel region of the transistor through a dielectric layer such as silicon oxide. The drain of the NMOS transistor T10 is coupled to the bit line BL0.
To sense whether a bit cell contains either a 0 or 1, a voltage is applied to the word line and if a transistor is coupled between the bit line and the word line at the bit cell being read, then current flows from the bit line through the transistor to ground. The detection of current through the NMOS transistor is achieved using a sense amplifier coupled to the bit line. Typically the presence of a transistor coupled between the word line and the bit line, which results in current flow being sensed on the bit line when a voltage is applied to the word line, corresponds to a 0 being stored in the bit cell.
A prior art diffusion ROM array 200 layout is shown in FIG. 2a. The prior art diffusion array 200 shows an array which has not been programmedxe2x80x94or it could be viewed as a diffusion array where all of the bit cells are programmed such that there are no transistors coupling any of the bit lines to any of the word lines, and hence all of the bit cells are programmed such that they store a data bit of 1. The operation of these ROMs is more clearly illustrated in connection with FIG. 2b below.
The layout shown in FIG. 2b shows a prior art diffusion ROM 201 where N+ diffusion has been used to program the ROM such that it corresponds to the architecture shown in FIG. 1. The word lines (WL0-WL3) are typically formed of polysilicon. The contacts 202 which are present for each bit cell (see, Node 001 thru Node 423 where each node corresponds to two bit cells) are also typically formed of using a metal interconnect to the N+ node diffusion area. Each node has a first region 204, which is a node diffusion region that is used to form a drain region. It should be noted that, as shown in FIG. 2a, the node diffusion region 204 is present at each node regardless of whether a transistor has been formed to couple the bit line to a word line.
Each of the bit cells is coupled to one of the bit lines (BL1-BL4) by a contact 202. Again it should be noted that, as shown in FIG. 2a, the contact 202 coupling the bit line to a node diffusion region is present at each node regardless of whether a transistor has been formed to couple the bit line to a word line. The bit lines are typically formed of metal. The VSS (Gnd) lines are typically formed using N+ diffusion into the P type substrate 203.
In the prior art diffusion ROM 201 (FIG. 2b) an NMOS transistor can be formed at any of the nodes of the ROM by extending the N+ diffusion from the node diffusion area 204 through the contact 202 connected to the bit line. Specifically, as shown in FIG. 2b the dotted lines 205 show regions where N+ diffusion into the underlying substrate forms NMOS transistors. The N+ diffusion extends the node diffusion region 204 to form a drain which is adjacent to the word line and further a source 206 is formed in the substrate by diffusing N+ into the substrate in the area between the word line and the Vss (gnd) area where N+ diffusion is also present. The word line acts as a gate, which is electrically coupled through a dielectric, with a channel region of the NMOS transistor.
FIG. 2b shows transistors formed between bit line BL1 and word line WL1, and bit line BL0 and word line WL2 for example. It should be noted that the contact 202 and node diffusion area 204 can be used to create the NMOS transistors to adjacent word lines. For example, at node 401, bit line (BL4), and the diffusion region is used to create bit line NMOS transistors to WL0 and to WL1.
FIG. 2c shows a cross section of FIG. 2b taken along Line Axe2x80x94A at the bit line BL0. It should be noted that FIG. 2c is not to scale and is provided for generally illustrating the lay out of different elements of the ROM. In this case, the substrate 203 is a P type silicon substrate. Node 001 is shown having a node diffusion area 204 with N+ diffusion. This region 204 is present at each of the cells whether a transistor is coupled between the corresponding bit line and a word line. Areas 210 are shown adjacent to the node diffusion region 204 of node 001, and adjacent to the node diffusion region 204 of node 023. The regions 210 are areas of N+ diffusion; thus areas 210 in combination with areas 204 form a drain region for an NMOS transistor. Regions 212 are also areas with N+ diffusion. These regions 212 form sources for the NMOS transistors and these sources are coupled to Vss (gnd). The regions 213 form channels between the regions 210 and 212. The channel region can conduct electrical current when a voltage is applied to the adjacent word line, and is not conductive when no voltage is present on the word line. The cross sectional view of FIG. 2c shows transistors T10 (coupling BL0 to WL1) and T20 (coupling BL0 to WL2) as shown in FIG. 1. The word lines WL1 and WL2 act as gates for the transistors, and are electrically coupled, via an intervening gate oxide dielectric material 215 with the channel regions 213, such that when a voltage is applied to the word line the channel regions 213 become conductive, as discussed above.
FIG. 2d shows a cross section of FIG. 2b taken along Line Bxe2x80x94B, i.e. along bit line BL3. As shown in FIG. 1, and FIGS. 2b and 2d no NMOS transistors are formed between the bit line BL3 and any of the word lines WL0-WL3. Although no NMOS transistors are formed along bit line BL3, each bit line still has a node diffusion region 204 with N type diffusion and a contact 202. Thus, the bit cell region 215 in the substrate 203 includes both the N type conductivity area of the node diffusion area 204 and the dielectric isolation region 209.
As shown above, the prior art ROM bit cells require the presence of the node diffusion area 204 and a contact 202, so that the ROM array can be programmed to achieve the desired connectivity which occurs when the diffusion node is extended during the programming of the ROM. For more advanced processes the node diffusion region 204, which is sometimes referred to as an xe2x80x9cislandxe2x80x9d, has a minimum area requirement specified by process design rules that are intended to ensure a high yield. This minimum area process rules will limit the minimum size of a ROM bit cell and limits the minimum area of the complete array of bit cells of the ROM. An example of this is shown in FIG. 2e and FIGS. 3a-c. Specifically, it can be seen that a minimum node diffusion area 207 has a significant effect on the overall size of the bit cells and the overall sized of the ROM. FIGS. 3a-c illustrate that the minimum node diffusion area 207 can take on various aspect ratios regarding the length and width of the node diffusion area.
The present invention is directed to a ROM which allows for a reduced size by forming the ROM such that a contact and a node diffusion region are not present at those nodes where a transistor is not coupling a bit line to a word line. In one embodiment, a ROM for storing information, includes a substrate having a plurality of bit cell regions formed in substrate. Proximate to the substrate are a plurality of columns of bit lines and a plurality of rows of word lines. The bit lines and word lines form intersection areas which are nodes that correspond to the plurality of bit cell regions. The embodiment includes a first transistor formed in a first bit cell region, which corresponds a first node, wherein a first bit line at the first node is coupled to the first transistor by a first contact. At a second node a second bit line is separated from a second bit cell region by an insulating layer.
In another embodiment a ROM for storing information, includes a substrate having a plurality of bit cell regions formed in substrate. A plurality of columns of bit lines are disposed proximate to the substrate, and a plurality of rows of word lines are disposed proximate to the substrate. The bit lines and word lines have intersection areas which form nodes that correspond to the plurality of bit cell regions formed in the substrate. A first bit cell region, which corresponds to a first node, has a first transistor, and a first bit line at the first node is coupled to the first transistor by a contact. The embodiment further includes a second bit cell region which corresponds to a second node, wherein the second bit cell region consists substantially of an isolating dielectric material.
In another embodiment a ROM includes an array of bit cells. The array includes a first bit cell which stores a first type of information, and the bit cell includes a first bit cell region disposed in a substrate. The first bit cell region includes a first region which has a first conductivity type such that it forms a drain, and includes a second region of a second conductivity type which is adjacent to the first region and forms a channel, and includes a third region which has the first conductivity type and forms a source. The array also includes a second bit cell which stores a second type of information, and includes a second bit cell region disposed in a substrate. The second bit cell region consists of a dielectric isolation region.